OVERCOMING THE CIRCUIT DESIGN CHALLENGES IN NANOSCALE SRAMs

Most microprocessors use large on-chip SRAM caches to bridge the performance gap between the processor and the main memory. Due to their growing embedded applications coupled with the technology scaling challenges, considerable attention is given to the design of low-power and high-performance SRAMs. However, there are many challenges in the design of both embedded and stand-alone SRAMs, such as, the estimation and optimization of stand-by power, design of high-speed peripheral circuits, and design of robust circuits for low-voltage operation. Further, as the technology continues scaling into the nanometer domain, controlling the variation in device parameters during fabrication becomes a great challenge. Variations in process parameters, such as, oxide thickness, channel length, channel width and dopant concentration can result in large variations in threshold voltage. This in turn is expected to severely affect the functionality of the minimum geometry transistors that are commonly used in SRAM designs. Our studies of new memory and peripheral circuits have shown significant promise in terms of power, speed and robustness. In this research, we address the following problems: Circuit techniques to estimate and simultaneously reduce gate leakage and sub-threshold leakage Process variations tolerant design approaches to reliably sense and amplify the bitlines with a minimum discharge providing a fast and accurate readout at low power